Need some information about a CPU

[freak]

I have these two processors:
- AMD Athlon 64 X2 Dual-Core (Brisbane G1) 4800+ (2.5 Ghz), 65nm
- Intel Core2 Duo P7350 @ 2.0 Ghz

Now I need to find out what kind of branch prediction these processors are using (type of predictors, buffer sizes etc). So far I only found vague second hand information. Is there some kind of official specification that contains these things? I need something that i can quote, so second hand information in articles or wikipedia entries doesn't cut it.

Does anybody have some hints for me? (or knows where I best ask this kind of question) ?

[Rings]

what about asking the original vendors ?

if you use for education (or 'DiplomArbeit' for quoting)
they will often give these information for free.

[Derek]

Try googling 'intel specifications', they have loads of details there. It might take a bit of digging out but it's a start. I had a quick look and didn't actually find your chip which was strange seeing as it's Intel's own site but I may of missed it.

[RASHAD]

@freak
See the next URL
Download the DataSheet and see if you will find your request
Or you have to go with Rings

Good luck

http://ark.intel.com/Product.aspx?id=3 ... cture.pdf

[Trond]

Look in the "Intel® 64 and IA-32 Architectures Optimization Reference Manual".

[Shardik]

- AMD Athlon 64 X2 Dual-Core (Brisbane G1) 4800+ (2.5 Ghz), 65nm

http://support.amd.com/us/Processor_Tec ... 2.pdf[code]• 64-Kbyte 2-Way Associative ECC-Protected
L1 Data Caches
– Two 64-bit operations per cycle, 3-cycle latency
• 64-Kbyte 2-Way Associative Parity-Protected
L1 Instruction Caches
– With advanced branch prediction
• 16-Way Associative ECC-Protected
L2 Caches
– Exclusive cache architecture—storage in addition
to L1 caches
– Up to 1 Mbyte per L2 cache[/code]

[Thorium]

I have these two processors:
- AMD Athlon 64 X2 Dual-Core (Brisbane G1) 4800+ (2.5 Ghz), 65nm
- Intel Core2 Duo P7350 @ 2.0 Ghz

Now I need to find out what kind of branch prediction these processors are using (type of predictors, buffer sizes etc). So far I only found vague second hand information. Is there some kind of official specification that contains these things? I need something that i can quote, so second hand information in articles or wikipedia entries doesn't cut it.

Intel does not explain there branch predictions in detail. However there are some information in the Optimization Manual: http://www.intel.com/Assets/PDF/manual/248966.pdf
Take a look at: 2.1.2.1: Branch Prediction Unit
and 3.4.1: Branch Prediction Optimization

[Rescator]

Isn't it possible to query cache info through WMI or similar?

[Thorium]

Isn't it possible to query cache info through WMI or similar?

It is, but he did not asked about the cache.

[Trond]

However there are some information in the Optimization Manual: http://www.intel.com/Assets/PDF/manual/248966.pdf

What I said.

[freak]

Thanks everyone for the help.

Its not really a crucial piece of information, so i am not going to make an official request to the vendors. It would have been more of a "nice to know" side note anyway.

[doctorized]

You can also check: http://crystalmark.info/?lang=en and take a look at CrystalCPUID's source code.