Problem with 128 bit registers (XMM)

[dangerfreak]

I was just messing around with 128 bit registers and can't explain, why I got the following syntax error:

Code: Select all

EnableExplicit

Global *buffer
*buffer=AllocateMemory(10)

!MOVDQA xmm1,DQWORD [p_buffer] ; works!

EnableASM
MOVDQA xmm1,dqword [p_buffer] ; syntax error???
DisableASM

FreeMemory(*buffer)

Why does it work with "!", but not with "enableASM"?

[STARGÅTE]

I think EnableASM do not check for all ASM instructions, just for the basic ones.
If you put a ! before the line, the whole line is forwarded to the assembler.
Without the !, the lines will also passed through the PB compiler.

As an additional note:
MOVDQA will not work on an allocated memory by PureBasic!
MOVDQA needs an 16-byte-aligned source/destination, which is not guaranteed by AllocateMemory()!

[Fred]

May be we should remove the EnableASM block, as it's more confusing than useful. '!' is better IMHO to pass directly the whole line to the ASM

[juergenkulow]

Which ASM commands are in pbcompiler.exe and which valid ASM commands are missing there and trigger false error messages?

[Fred]

I didn't upated the asm since a while (means about 20 years) so it's expected it didn't work as expected. I can take a closer look to update it and may be put it on GitHub if some of you want to take a look.

[idle]

I didn't upated the asm since a while (means about 20 years) so it's expected it didn't work as expected. I can take a closer look to update it and may be put it on GitHub if some of you want to take a look.

I added loads of asm keywords to the ide when he was open sourced and had asked you if you could add them to the compiler some time.

[juergenkulow]

Code: Select all

x64op ADC ADD ADDPD ADDPS ADDSD ADDSS ADDSUBPD ADDSUBPS AND ANDNPD ANDNPS ANDPD ANDPS BLENDPD BLENDPS BSF BSR BSWAP BT BTC BTR BTS CALL CALLF CBW CWDE CDQE CLC CLD CLFLUSH CLI CLTS CMC CMOVB CMOVNAE CMOVC CMOVBE CMOVNA CMOVL CMOVNGE CMOVLE CMOVNG CMOVNB CMOVAE CMOVNC CMOVNBE CMOVA CMOVNL CMOVGE CMOVNLE CMOVG CMOVNO CMOVNP CMOVPO CMOVNS CMOVNZ CMOVNE CMOVO CMOVP CMOVPE CMOVS CMOVZ CMOVE CMP CMPPD CMPPS CMPS CMPSB CMPS CMPSW CMPSD CMPSQ CMPSD CMPSS CMPXCHG CMPXCHG8B CMPXCHG16B COMISD COMISS CPUID CRC32 CVTDQ2PD CVTDQ2PS CVTPD2DQ CVTPD2PI CVTPD2PS CVTPI2PD CVTPI2PS CVTPS2DQ CVTPS2PD CVTPS2PI CVTSD2SI CVTSD2SS CVTSI2SD CVTSI2SS CVTSS2SD CVTSS2SI CVTTPD2DQ CVTTPD2PI CVTTPS2DQ CVTTPS2PI CVTTSD2SI CVTTSS2SI CWD CDQ CQO DEC DIV DIVPD DIVPS DIVSD DIVSS DPPD DPPS EMMS ENTER EXTRACTPS F2XM1 FABS FADD FADDP FBLD FBSTP FCHS FCLEX FCMOVB FCMOVBE FCMOVE FCMOVNB FCMOVNBE FCMOVNE FCMOVNU FCMOVU FCOM FCOM2 FCOMI FCOMIP FCOMP FCOMP3 FCOMP5 FCOMPP FCOS FDECSTP FDIV FDIVP FDIVR FDIVRP FFREE FFREEP FIADD FICOM FICOMP FIDIV FIDIVR FILD FIMUL FINCSTP FINIT FIST FISTP FISTTP FISUB FISUBR FLD FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL FMULP FNCLEX FNDISI nop FNENI nop FNINIT FNOP FNSAVE FNSETPM nopFNSTCW FNSTENV FNSTSW FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR FS FSAVE FSCALE FSIN FSINCOS FSQRT FST FSTCW FSTENV FSTP FSTP1 FSTP8 FSTP9 FSTSW FSUB FSUBP FSUBR FSUBRP FTST FUCOM FUCOMI FUCOMIP FUCOMP FUCOMPP FWAIT WAIT FXAM FXCH FXCH4 FXCH7 FXRSTOR FXSAVE FXTRACT FYL2X FYL2XP1 GETSEC GS HADDPD HADDPS HINT_NOP HLT HSUBPD HSUBPS IDIV IMUL IN INC INS INSB INS INSW INS INSD INSERTPS INT INT1 ICEBP INTO INVD INVEPT INVLPG INVVPID IRET IRETD IRETQ JB JNAE JC JB JNAE JC JBE JNA JBE JNA JECXZ JRCXZ JL JNGE JL JNGE JLE JNG JLE JNG JMP JMPF JNB JAE JNC JNB JAE JNC JNBE JA JNBE JA JNL JGE JNL JGE JNLE JG JNLE JG JNO JNP JPO JNP JPO JNS JNZ JNE JNZ JNE JO JP JPE JP JPE JS JZ JE JZ JE LAHF LAR LDDQU LDMXCSR LEA LEAVE LFENCE LFS LGDT LGS LIDT LLDT LMSW LOCK LODS LODSB LODS LODSW LODSD LODSQ LOOP LOOPNZ LOOPNE LOOPZ LOOPE LSL LSS LTR MASKMOVDQU MASKMOVQ MAXPD MAXPS MAXSD MAXSS MFENCE MINPD MINPS MINSD MINSS MONITOR MOV MOVAPD MOVAPS MOVBE MOVD MOVQ MOVD MOVQ MOVD MOVQ MOVD MOVQ MOVDDUP MOVDQ2Q MOVDQA MOVDQU MOVHLPS MOVHPD MOVHPS MOVLHPS MOVLPD MOVLPS MOVMSKPD MOVMSKPS MOVNTDQ MOVNTI MOVNTPD MOVNTPS MOVNTQ MOVQ MOVQ2DQ MOVS MOVSB MOVS MOVSW MOVSD MOVSQ MOVSD MOVSHDUP MOVSLDUP MOVSS MOVSX MOVSXD MOVUPD MOVUPS MOVZX MPSADBW MUL MULPD MULPS MULSD MULSS MWAIT NEG NOP NOT OR ORPD ORPS OUT OUTS OUTSB OUTS OUTSW OUTS OUTSD PACKSSDW PACKSSWB PACKUSWB PADDB PADDD PADDQ PADDSB PADDSW PADDUSB PADDUSW PADDW PALIGNR PAND PANDN PAUSE PAVGB PAVGW PBLENDW PCMPEQB PCMPEQD PCMPEQW PCMPESTRI PCMPESTRM PCMPGTB PCMPGTD PCMPGTW PCMPISTRI PCMPISTRM PEXTRB PEXTRD PEXTRQ PEXTRW PINSRB PINSRD PINSRQ PINSRW PMADDWD PMAXSW PMAXUB PMINSW PMINUB PMOVMSKB PMULHUW PMULHW PMULLW PMULUDQ POP POPCNT POPF POPFQ POR PREFETCHNTAPREFETCHT0 PREFETCHT1 PREFETCHT2 PSADBW PSHUFD PSHUFHW PSHUFLW PSHUFW PSLLD PSLLDQ PSLLQ PSLLW PSRAD PSRAW PSRLD PSRLDQ PSRLQ PSRLW PSUBB PSUBD PSUBQ PSUBSB PSUBSW PSUBUSB PSUBUSW PSUBW PUNPCKHBW PUNPCKHDQ PUNPCKHQDQ PUNPCKHWD PUNPCKLBW PUNPCKLDQ PUNPCKLQDQ PUNPCKLWD PUSH PUSHF PUSHFQ PXOR RCL RCPPS RCPSS RCR RDMSR RDPMC RDTSC RDTSCP REP REPNZ REPNE REPZ REPE RETF RETN REX REX.B REX.R REX.RB REX.RX REX.RXB REX.W REX.WB REX.WR REX.WRB REX.WRX REX.WRXB REX.WX REX.WXB REX.X REX.XB ROL ROR ROUNDPD ROUNDPS ROUNDSD ROUNDSS RSM RSQRTPS RSQRTSS SAHF SAL SHL SAL SHL SAL SHL SAL SHL SAL SHL SAL SHL SAR SBB SCAS SCASB SCAS SCASW SCASD SCASQ SETB SETNAE SETC SETBE SETNA SETL SETNGE SETLE SETNG SETNB SETAE SETNC SETNBE SETA SETNL SETGE SETNLE SETG SETNO SETNP SETPO SETNS SETNZ SETNE SETO SETP SETPE SETS SETZ SETE SFENCE SGDT SHL SAL SHL SAL SHL SAL SHL SAL SHL SAL SHL SAL SHLD SHR SHRD SHUFPD SHUFPS SIDT SLDT SMSW SQRTPD SQRTPS SQRTSD SQRTSS STC STD STI STMXCSR STOS STOSB STOS STOSW STOSD STOSQ STR SUB SUBPD SUBPS SUBSD SUBSS SWAPGS SYSCALL SYSENTER SYSEXIT SYSRET TEST UCOMISD UCOMISS UD UD2 UNPCKHPD UNPCKHPS UNPCKLPD UNPCKLPS VERR VERW VMCALL VMCLEAR VMLAUNCH VMPTRLD VMPTRST VMREAD VMRESUME VMWRITE VMXOFF VMXON WBINVD WRMSR XADD XCHG XGETBV XLAT XLATB XOR XORPD XORPS XRSTOR XSAVE XSETBV 

[naf]

I tried all possible ways and could not get started using the 128-bit registers of SSE2.
I agree with Fred, "enableASM" seems to make things worse.

Code: Select all

;comment
structure p4 : w.f : x.f : y.f : z.f : endstructure
global ppp.p4
dataSection
	q4: ; like a virtual table
	Data.f 1.1, 2.2, 3.3, 4.4
	endDataSection
!USE64
! Align 16
! v1: dd 1.1, 1.1, 1.1, 1.1
; i.e. define double-word, define 32b "float"
!	movups xmm0, dqword [l_q4]
!	movaps xmm0, dqword [v1]
!	movups xmm0, dqword [p_ppp]
; All 3 seem ok for yasm's first pass only.
; 2nd pass --> weird ERROR "invalid memory access" on the first line, a comment.
end
	

My goal: I write an interesting 3d modeler and would like to speed up the rendering with SSE2's packed data ability, mainly + - * / between 4d float values, all done in a single execution cycle. The vectors are in a "structure" form. They could also be in another form, like array (of float) or buffer (of 4 floats).
Beyond this simple game, has anyone an idea how to integrate CUDA parallel computing code (in C language) into purebasic?
Thank you.

<windows 10 home, PB 6.20 x64, MSI GP72 2QE, intel i7, Nvidia GTX950M>

[Demivec]

Does the structure 'p4' or the data table 'q4' have to be aligned also?

[SMaag]

here are the link to my 4D Vector Library, there you can look how to use 4D SEE commands
https://github.com/Maagic7/PureBasicFra ... VECTORf.pb

and here a collection of important ASM Macros
https://github.com/Maagic7/PureBasicFra ... Macros.pbi

[SMaag]

Code: Select all

Global Vec.Vector4

DataSection
  q1: : Data.f 1.1, 2.2, 3.3, 4.4	
EndDataSection

Procedure LoadVec4FromDataSection(*vec.Vector4, *Data)
  
  !mov rax, [p.p_Data]
  !movups xmm0, [rax]
  
  !mov rdx, [p.p_vec]
  !movups [rdx], xmm0
  
EndProcedure

LoadVec4FromDataSection(Vec, ?q1)

Debug vec\x
Debug vec\y
Debug vec\z
Debug ""

DataSection
	!vec2: dd 1.1, 1.1, 1.1, 1.1
EndDataSection

!movups xmm1, [vec2]
!lea rax, [v_Vec]
!movups [rax], xmm1

Debug vec\x
Debug vec\y
Debug vec\z
Debug ""

!movups xmm1, [l_q1]
!lea rax, [v_Vec]
!movups [rax], xmm1

Debug vec\x
Debug vec\y
Debug vec\z
Debug ""

[idle]

if you want aligned you can use these functions

Code: Select all

Procedure.i AllocateAligned(size.i, align.i)
  Protected *mem, *aligned
  *mem = AllocateMemory(size + align+8)
  If *mem
    *aligned = (*mem + 8 + align - 1) & ~(align-1)
    PokeI(*aligned - SizeOf(Integer), *mem) 
    ProcedureReturn *aligned
  EndIf
  ProcedureReturn 0
EndProcedure

Procedure FreeAligned(*aligned)
  If *aligned
    Protected *original = PeekI(*aligned - SizeOf(Integer))
    FreeMemory(*original)
  EndIf
EndProcedure 

Procedure MemorySizeAligned(mem,aligned) 
  sz = MemorySize(PeekI(mem-SizeOf(integer)))
  ProcedureReturn sz-8-SizeOf(Integer)-(sz&(aligned-1)) 
EndProcedure   

Structure vec4 
  x.f
  y.f
  z.f
  w.f 
EndStructure 

*v.vec4 = AllocateAligned(128,16) 
!mov rax, [p_v]
!movaps xmm1, dqword [rax] 
Debug MemorySizeAligned(*v,16) 

[naf]

Does the structure 'p4' or the data table 'q4' have to be aligned also?

Older gfx cards needed it. Later they accepted unaligned.

Code: Select all

movaps  movups

a and u mean aligned/unaligned.