Convert C code

[Otrebor]

I need to convert 2 lines of C code
#1

Code: Select all

fr= a= (ff= (fa= a)+(fb= b)+(ff>>8&1)) ; //C code

 fa=a
 fb=b
 ff=(ff>>8&1)+fa+fb
 a=ff
 fr=a  

#2

Code: Select all

fr= a= (ff= (fa= a)+(fb= ~b)+(ff>>8&1^1)) ;// C code

  fb=~b
  fa=a
  ff=fa+fb+((ff>>8&1)!1)
  a=ff
  fr=a 

The 2 lines above are part of Z80 instructions ADC() and SBC(). Currently my interpretation pass almost all tests, but i found that in one specific test it is fail. Please, can someone see what is wrong?

[infratec]

Hm... maybe you need an additional brace, C has partly a different order for executing.

Code: Select all

fa = a
fb = b
ff = fa + fb + ((ff >> 8) & 1)
a = ff
fr = a

Code: Select all

fa = a
fb = ~b
ff = fa + fb + (((ff >> 8) & 1) ! 1)
a = ff
fr = a

And you need the right variable types .a and .u
I think the sign stuff is done by the emulator itself.
Can I ask which emu it is?

I wrote a Sharp MZ700 Emulator and used first MZ80 cause of the speed, but then I needed to change over to RAZE, cause of the bank switching.

[Otrebor]

infratec, thank you. Unfortunately stil fail...

Hm... maybe you need an additional brace, C has party a different order fr executing.

Yes , the order of executing (operators priorities) cause me a lot the problem while converting this code years ago:

https://github.com/antoniovillena/ticks

Can I ask which emu it is?

The emulator that i wrote is simpleTK (ZX Spectrum/TK90X). "Ticks" and PureBasic inspired me to start the emulator.
At the moment the z80 in my emulator is very stable and, as i said, pass almost all tests...only with "z80 all instructions exerciser" test it fail.

Nice that you wrote Sharp MZ700 emulator, although not very well know in my country.

[wilbert]

It's hard to tell without seeing more code.
The C conversion looks fine.
It's indeed very important what variable types you used for these variables.
A wrong variable type can cause problems.

Are you sure the problem is with these two instructions ?
I don't know what "z80 all instructions exerciser" does but the Zilog Z80 processor does have some undocumented opcodes.
If it checks for those and you haven't implemented them that might also cause problems.

[IceSoft]

It's indeed very important what variable types you used for these variables.
A wrong variable type can cause problems.

And some example input/output values/results for validation of the PB code

[infratec]

Yes, please give us the values of all variables when it fails
and also the expected results.

[infratec]

Please try this:

Code: Select all

fa = a
fb = b
ff = fa + fb + ((ff >> 8) & 1)
a = ff & $FF
fr = ff

fr can make a difference
ff looks good it's a + value + carry

Because

Code: Select all

define.a a, b, c, d, e, h, l
define.u pc, sp, fa, fb, ff, fr

[Otrebor]

Hi

Code: Select all

my definitions
Global pc.u, pc_.u, sp.u, mp.u, t.u, u.u, ff.u, ff_.u, fa.u, fa_.u, fb.u, fb_.u, fr.u, fr_.u

Macro ADC(b)            
 TstatesDelay(pc-1)  
 addst(4)
 fa=a
 fb=b
 ff=(ff>>8&1)+fa+fb
 a=ff
 fr=a  
 _f3Updated = #True 
EndMacro

Macro z80() 
  Select RByte((pc-1)&$FFFF)  ; RByte = read byte
  
  ;...
    Case $88                             ;ADC A,B
      ADC(b)
      ih=1
    Case $89                             ;ADC A,C
      ADC(c)
      ih=1
    Case $8A                             ;ADC A,D
      ADC(d)
      ih=1
    Case $8B                             ;ADC A,E
      ADC(e)
      ih=1
    Case $8C                             ;ADC A,H // ADC A,IXh // ADC A,IYh
      If ih 
        ADC(h)
      ElseIf iy 
        ADC(yh)
      Else
        ADC(xh)
      EndIf
      ih=1    
    Case $8D                             ;ADC A,L // ADC A,IXl // ADC A,IYl
      If ih  
        ADC(l)
      ElseIf iy 
        ADC(yl)
      Else
        ADC(xl)
      EndIf
      ih=1  
    Case $8E                             ;ADC A,(HL) // ADC A,(IX+d) // ADC A,(IY+d)
      If ih 
        ADC(RByte(l|h<<8)):If (l|h<<8) =RAMR:menu=6800:EndIf
        TstatesDelay(l|h<<8)
        addst(3)
      ElseIf iy 
        t=((RByte(pc)!128)-128+(yl|yh<<8));&65535
        ADC(RByte(t)):If t =RAMR:menu=6800:EndIf
        TstatesDelay(pc)
        addst(3)
        repst(pc,1,5) 
        TstatesDelay(t)
        addst(3)
        pc+1
      Else
        t=((RByte(pc)!128)-128+(xl|xh<<8));&65535
        ADC(RByte(t)):If t =RAMR:menu=6800:EndIf
        TstatesDelay(pc)
        addst(3)
        repst(pc,1,5)
        TstatesDelay(t)
        addst(3)
        pc+1
      EndIf 
      ih=1
;...

The macro ADC() is used in all combinations. The same to SBC().
The Z80 part is totally based in the previous link i posted in github, with some modifications after i implemented contention.
When i converted the code, i was worried about with parameter 'b' used in the macro should be confused with b of BC register, but not the case...




Here another test, with result OK:



infratec, still fail.
wilbert, i implement undocumented opcodes.

Well...i need to think in another way to represent the flags in these opcodes.
Thanks everyone

[infratec]

I think you search at the wrong place.

; <adc,sbc> hl,<bc,de,hl,sp> (38,912 cycles)
adc16: db 0ffh ; flag mask
tstr 0edh,042h,0,0,0832ch,04f88h,0f22bh,0b339h,07e1fh,01563h,0d3h,089h,0465eh
tstr 0,038h,0,0,0,0,0,0f821h,0,0,0,0,0 ; (1024 cycles)
tstr 0,0,0,0,0,0,0,-1,-1,-1,0d7h,0,-1 ; (38 cycles)
db 0d4h,08ah,0d5h,019h ; expected crc
tmsg '<adc,sbc> hl,<bc,de,hl,sp>....'

(expected crc is the crc shown in your failed image)

This concerns to

case 0x4a: ADCHLRR(b, c); break; // ADC HL,BC
case 0x5a: ADCHLRR(d, e); break; // ADC HL,DE
case 0x6a: ADCHLRR(h, l); break; // ADC HL,HL

ADCHLRR and not ADC

[Otrebor]

You are right!!
I will investigate...

Thank you!