[Implemented] switch var1, var2

coma · Post by **coma** » Thu Mar 04, 2004 3:26 pm

if was an example to show how things may be "curious".
sometimes, the empty loop take more time than the other one.

Psychophanta · Post by **Psychophanta** » Thu Mar 04, 2004 3:35 pm

coma:
result for your last question was: 156 / 109 , other times 140 / 110 ...

Freak:
Yes, i know, but i prefer real ASM better than inlined

Post by **Dare2** » Thu Mar 04, 2004 4:13 pm

hehe. I had the empty loop come 2nd a few times as well.

Deduction - Bloat your code! It may run faster!

techjunkie · Post by **techjunkie** » Thu Mar 04, 2004 4:27 pm

Psychophanta wrote:result is: 110 / 94 / 125 / 46

The result on my Dell Dimension 8200 (P4 2GHz) is,

203 / 141 / 1140 / 32

Why is the t2 example so slow? Hmmmm...

Psychophanta · Post by **Psychophanta** » Thu Mar 04, 2004 7:05 pm

techjunkie wrote

Why is the t2 example so slow? Hmmmm...

I don't know, but it seem one more of the Intel incoherences; now with XCHG instruction, and AMD seem to be less incoherent with this instruction.

Have you tried Intel i386 LOOP asm instruction? it is a shame

coma · Post by **coma** » Thu Mar 04, 2004 7:17 pm

XCHG eax,ebx is very fast.
it's "XCHG eax,mem" that is slow.

Psychophanta · Post by **Psychophanta** » Thu Mar 04, 2004 9:11 pm

XCHG eax,ebx is very fast.
it's "XCHG eax,mem" that is slow.

Which demonstrates still more incoherence

Trond · Post by **Trond** » Fri Aug 28, 2009 12:22 pm

XHCG with memory operand always asserts a bus lock to make the instruction atomic. That's why it's slow.

Since we have the new structure assignment, I request this feature to work for structured types as well.

talisman · Post by **talisman** » Sun Aug 30, 2009 10:39 am

Trond wrote:XHCG with memory operand always asserts a bus lock to make the instruction atomic. That's why it's slow.

Since we have the new structure assignment, I request this feature to work for structured types as well.

...and your reply came in just 5 years slow

DarkDragon · Post by **DarkDragon** » Sun Aug 30, 2009 10:57 am

talisman wrote:
Trond wrote:XHCG with memory operand always asserts a bus lock to make the instruction atomic. That's why it's slow.

Since we have the new structure assignment, I request this feature to work for structured types as well.
...and your reply came in just 5 years slow

He wants it for structured types

. So thats the right topic.

John Puccio · Post by **John Puccio** » Tue Sep 01, 2009 5:38 am

Trond wrote:Since we have the new structure assignment, I request this feature to work for structured types as well.

+1 @Trond's request. I think that would be really neat!

blueznl · Post by **blueznl** » Tue Sep 01, 2009 8:22 am

Me too!