Japanese ANIME quality up on streming

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oryaaaaa
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Joined: Mon Jan 12, 2004 11:40 pm
Location: Okazaki, JAPAN

Japanese ANIME quality up on streming

Post by oryaaaaa »

Hello, This tips is Japanese ANIME quality up on streming.

I released open source super-low-jitter program for Japanese anime video streaming.
But many enginners said "Please post PureBasic forum tips."

Run this code, Debugger output Generated codes.
Copy and Paste in PB editor, and Run.

required CPU instruction
MMX(Integer) Intel CPU
RDRAND Intel 3th Generation IvyBridge
BLSR Intel 4th Generation Haswell
RDSEED Intel 6th Generation SkyLake

Thank you for review's many JPLAY users.
JPLAY forum English - Computer Audio - Pink HQ + Minorityclean

Code: Select all

Debug "; RDSEED BLSR CPU reg. Stabilizer for network streaming anime video"
Debug "; from ExtremeStabilizer 105 (2023 01 05)"
Debug "; Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"
Debug "; Design based by Military LAB-AI designed (Customized  Hiroyuki Yokota)"
Debug "; Executable Format Windows/Console/DLL and CPU with MMX"
Debug ";"

NewMap Reg64.s()
Reg64("AX")="Rax"
Reg64("BX")="Rbx"
Reg64("CX")="Rcx"
Reg64("DX")="Rdx"
Reg64("SP")="Rsp"
Reg64("SI")="Rsi"
Reg64("BP")="Rbp"
Reg64("DI")="Rdi"
Reg64("R8")="R8"
Reg64("R9")="R9"
Reg64("R10")="R10"
Reg64("R11")="R11"
Reg64("R12")="R12"
Reg64("R13")="R13"
Reg64("R14")="R14"
Reg64("R15")="R15"

NewMap Reg64A.s()
Reg64A("AX")="Rax"
Reg64A("DX")="Rdx"
Reg64A("SP")="Rsp"
Reg64A("SI")="Rsi"
Reg64A("R9")="R9"
Reg64A("R11")="R11"
Reg64A("R13")="R13"
Reg64A("R15")="R15"

NewMap Reg64B.s()
Reg64B("BX")="Rbx"
Reg64B("CX")="Rcx"
Reg64B("BP")="Rbp"
Reg64B("DI")="Rdi"
Reg64B("R8")="R8"
Reg64B("R10")="R10"
Reg64B("R12")="R12"
Reg64B("R14")="R14"

NewMap Reg16.s()
Reg16("Rax")="ax"
Reg16("Rbx")="bx"
Reg16("Rcx")="cx"
Reg16("Rdx")="dx"
Reg16("Rsp")="sp"
Reg16("Rsi")="si"
Reg16("Rbp")="bp"
Reg16("Rdi")="di"
Reg16("R8")="R8w"
Reg16("R9")="R9w"
Reg16("R10")="R10w"
Reg16("R11")="R11w"
Reg16("R12")="R12w"
Reg16("R13")="R13w"
Reg16("R14")="R14w"
Reg16("R15")="R15w"

NewMap Reg8.s()
Reg8("Rax")="al"
Reg8("Rbx")="bl"
Reg8("Rcx")="cl"
Reg8("Rdx")="dl"
Reg8("Rsp")="spl"
Reg8("Rsi")="sil"
Reg8("Rbp")="bpl"
Reg8("Rdi")="dil"
Reg8("R8")="R8b"
Reg8("R9")="R9b"
Reg8("R10")="R10b"
Reg8("R11")="R11b"
Reg8("R12")="R12b"
Reg8("R13")="R13b"
Reg8("R14")="R14b"
Reg8("R15")="R15b"

ForEach Reg64()
  Debug "Macro BLSR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !BLSR "+Reg64()+", "+Reg64()
  Next
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro MOV_"+Reg64()+"_Up_Down"
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  Debug "  !MOV "+Reg64()+", "+Reg64()
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  Debug "EndMacro"
  Debug ""
Next

Debug "Macro Set_CL1"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  ; cx = 1"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL8"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 8"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL64"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 64"
Debug "EndMacro"
Debug ""
Debug "Macro ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL1"
Debug "  MOVZX_Rcx"
Debug "  !MOVQ mm1, Rcx"
For Loop=1 To 16
  Debug "  !PSLLW mm0, mm1 ;"+Str(Loop)+" Left 1bit shift"
Next
Debug "  !MOVQ mm0, mm1"
For Roop=1 To 7
  For Loop=1 To 16
    Debug "  !PSLLW mm"+Str(Roop)+", mm0 ;"+Str(Loop)+" Left 1bit shift"
  Next
Next
Debug "EndMacro"
Debug ""

Debug "Macro SIMPLE_MOVE_REGISTERS_Up_and_Down"
ForEach Reg64A()
  Debug "  MOV_"+Reg64A()+"_Up_Down"
Next
ForEach Reg64B()
  Debug "  MOV_"+Reg64B()+"_Up_Down"
Next
Debug "EndMacro"
Debug ""

Debug "Macro MOVZX_Rcx"
Debug "  !MOVZX cx, cl"
Debug "  !MOVZX Rcx, cl"
Debug "  !MOVZX cx, cl"
Debug "EndMacro"
Debug ""
  
Dim Inst.s(3)
Inst(1) = "SMSW REG"
Inst(2) = "RDRAND REG"
Inst(3) = "RDSEED REG"
; Inst(4) = "HELL REG, REG"
; Inst(5) = "HALT REG, REG, REG"

For Roop=1 To 3
  Debug "Macro BeforeProcedureRegisters_"+StringField(Inst(Roop),1," ")+"_BLSR"
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ForEach Reg64A()
    Debug "  MOV_"+Reg64A()+"_Up_Down"
  Next
  Loop=0
  ForEach Reg64A()
    Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64A()
    Loop + 1
  Next
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !"+ReplaceString(Inst(Roop), "REG", Reg64A())
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  Loop=0
  ForEach Reg64A()
    Debug "  !MOVQ "+Reg64A()+", mm"+Str(Loop)
    Loop + 1
  Next
  ForEach Reg64A()
    Debug "  MOV_"+Reg64A()+"_Up_Down"
  Next
  Debug "  ;"
  ForEach Reg64B()
    Debug "  MOV_"+Reg64B()+"_Up_Down"
  Next
  Loop=0
  ForEach Reg64B()
    Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64B()
    Loop + 1
  Next
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !"+ReplaceString(Inst(Roop), "REG", Reg64B())
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  Loop=0
  ForEach Reg64B()
    Debug "  !MOVQ "+Reg64B()+", mm"+Str(Loop)
    Loop + 1
  Next
  ForEach Reg64B()
    Debug "  MOV_"+Reg64B()+"_Up_Down"
  Next
  Debug "  !EMMS"
  Debug "EndMacro"
  Debug ""
Next

Debug ";- PureBasicStart"
; Debug "CompilerIf #PB_Compiler_ExecutableFormat=#PB_Compiler_Console"
Debug "If OpenConsole("+Chr(34)+"RDSEED BLSR setup To General-purpose 64-bit registers."+Chr(34)+")"
Debug "  !StartStabilizer:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
; Debug "CompilerElseIf #PB_Compiler_ExecutableFormat=#PB_Compiler_DLL"
; Debug "ProcedureDLL CPU64regStabilizer()"
; Debug "CompilerElse"
; Debug "  !StartStabilizer:"
; Debug "  !NOP QWORD [Rip]"
; Debug "  !NOP QWORD [Rip]"
; Debug "CompilerEndIf"
; Debug "CompilerIf #PB_Compiler_ExecutableFormat=#PB_Compiler_Console"
Debug "  PrintN("+Chr(34)+"Setup ... RDSEED BLSR CPU reg. Stabilizer"+Chr(34)+")"
; Debug "CompilerEndIf"
For Roop=1 To 64
  Debug "  ; "+Str(Roop)+" Setup"
  Debug "  BeforeProcedureRegisters_SMSW_BLSR"
  Debug "  BeforeProcedureRegisters_RDSEED_BLSR" ; or RDRAND or remove
  Debug "  SIMPLE_MOVE_REGISTERS_Up_and_Down"
  Debug "  BLSR_Rcx_x64"
  Debug "  Set_CL64"
  Debug "  MOVZX_Rcx"
;   Debug "CompilerIf #PB_Compiler_OS=#PB_OS_Linux or #PB_Compiler_OS=#PB_OS_MacOS"
;   Debug "  !MOV_Rdi, Rcx"
;   Debug "CompilerEndIf"
  Debug "  !NOP QWORD [Rip+16]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !CALL QWORD PB_Delay"
  Debug "  !NOP QWORD [Rip-32]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
Next
Debug "  BeforeProcedureRegisters_SMSW_BLSR"
Debug "  BeforeProcedureRegisters_RDSEED_BLSR" ; or RDRAND or remove
Debug "  SIMPLE_MOVE_REGISTERS_Up_and_Down"
; Debug "CompilerIf #PB_Compiler_ExecutableFormat=#PB_Compiler_Console"
Debug "  PrintN("+Chr(34)+"Finished"+Chr(34)+")"
; Debug "CompilerEndIf"
Debug "  BLSR_Rax_x64"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL64"
Debug "  MOVZX_Rcx"
Debug "  !MOV Rax, Rcx"
Debug "  Set_CL8"
Debug "  !SHL Rax, cl"
; Debug "CompilerIf #PB_Compiler_OS=#PB_OS_Linux or #PB_Compiler_OS=#PB_OS_MacOS"
; Debug "  !MOV_Rdi, Rax"
; Debug "CompilerElse"
Debug "  !MOV Rcx, Rax"
; Debug "CompilerEndIf"
Debug "  !NOP QWORD [Rip+16]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !CALL QWORD PB_Delay"
Debug "  !NOP QWORD [Rip-32]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
; Debug "CompilerIf #PB_Compiler_ExecutableFormat=#PB_Compiler_Console"
Debug "  !JMP QWORD StartStabilizer"
Debug "  CloseConsole()"
Debug "EndIf"
; Debug "CompilerElseIf #PB_Compiler_ExecutableFormat=#PB_Compiler_DLL"
; Debug "EndProcedure"
; Debug "CompilerElse"
; Debug "  !JMP QWORD StartStabilizer"
; Debug "CompilerEndIf"
Debug "Delay(800)"
Debug "End"
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User avatar
oryaaaaa
Addict
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Posts: 825
Joined: Mon Jan 12, 2004 11:40 pm
Location: Okazaki, JAPAN

MajiorityCamisole ES112 release

Post by oryaaaaa »

MajiorityCamisole ES112 release.
Users said "very good".

PB Delay set 1 ms Timer Resolution.
this ES112 use API Sleep.

SIMPLE_MOVE_REGISTERS_Up_and_Down
The "MOV instruction up/down" in Rax and R8 means "electrical update to physical registers," which can be processed with low noise by avoiding transient phenomena if electricity is applied to the dedicated circuit in advance before operation. Also, benchmark test results will be better. (tranlated by DeepL)
  1. step 1
    BeforeProcedureRegisters_RDSEED_SHR
    Long time, this stabilizer enabled condision is "RDSEED SHR every 16384ms turn"
  • step 2
    BeforeProcedureRegisters_SMSW_BLSR
    BeforeProcedureRegisters_RDSEED_BLSR
    Low noise condision keep is "1st SMSW 2nd RDSEED"
  • step 3
    SIMPLE_MOVE_REGISTERS_Up_and_Down
  • step 4
    Sleep_(64) by RCX regisiters only
    This thread will switched others CPU cores.
  • Step 5
    2-4 loop process is 64 times repeate.
  • Step 6
    Sleep_(16384) and Jump Step 1
    Windows task switch time is 16ms, I stay 10 times delay.

Code: Select all

Debug "; MajiorityCamisole ExtremeStabilizer 112 (2023 01 23)"
Debug "; RDSEED BLSRx64 CPU reg. Stabilizer for network streaming anime video"
Debug "; Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"
Debug "; Design based by Military LAB-AI designed (Customized  Hiroyuki Yokota)"
Debug ""
Debug "MessageRequester("+Chr(34)+"END"+Chr(34)+","+Chr(34)+"Compiler options Executable Format Console And CPU With MMX"+Chr(34)+") : End"
Debug ""
!extrn PB_RandomSeed

Global NewList Reg64.s()
AddElement(Reg64()) : Reg64() ="Rax" : AddElement(Reg64()) : Reg64() ="Rbx"
AddElement(Reg64()) : Reg64() ="Rcx" : AddElement(Reg64()) : Reg64() ="Rdx"
AddElement(Reg64()) : Reg64() ="Rsp" : AddElement(Reg64()) : Reg64() ="Rsi"
AddElement(Reg64()) : Reg64() ="Rbp" : AddElement(Reg64()) : Reg64() ="Rdi"
AddElement(Reg64()) : Reg64() ="R8" : AddElement(Reg64()) : Reg64() ="R9"
AddElement(Reg64()) : Reg64() ="R10" : AddElement(Reg64()) : Reg64() ="R11"
AddElement(Reg64()) : Reg64() ="R12" : AddElement(Reg64()) : Reg64() ="R13"
AddElement(Reg64()) : Reg64() ="R14" : AddElement(Reg64()) : Reg64() ="R15"

Global NewList Reg64A.s()
AddElement(Reg64A()) : Reg64A() ="Rax" : AddElement(Reg64A()) : Reg64A() ="Rdx"
AddElement(Reg64A()) : Reg64A() ="Rsp" : AddElement(Reg64A()) : Reg64A() ="Rsi"
AddElement(Reg64A()) : Reg64A() ="R9" : AddElement(Reg64A()) : Reg64A() ="R11"
AddElement(Reg64A()) : Reg64A() ="R13" : AddElement(Reg64A()) : Reg64A() ="R15"

Global NewList Reg64B.s()
AddElement(Reg64B()) : Reg64B() ="Rbx" : AddElement(Reg64B()) : Reg64B() ="Rcx"
AddElement(Reg64B()) : Reg64B() ="Rbp" : AddElement(Reg64B()) : Reg64B() ="Rdi"
AddElement(Reg64B()) : Reg64B() ="R8" : AddElement(Reg64B()) : Reg64B() ="R10"
AddElement(Reg64B()) : Reg64B() ="R12" : AddElement(Reg64B()) : Reg64B() ="R14"

!RDRAND Rcx
!CALL QWORD PB_RandomSeed
RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())

NewMap Reg16.s()
Reg16("Rax")="ax" : Reg16("Rbx")="bx" : Reg16("Rcx")="cx" : Reg16("Rdx")="dx"
Reg16("Rsp")="sp" : Reg16("Rsi")="si" : Reg16("Rbp")="bp" : Reg16("Rdi")="di"
Reg16("R8")="R8w" : Reg16("R9")="R9w" : Reg16("R10")="R10w" : Reg16("R11")="R11w"
Reg16("R12")="R12w" : Reg16("R13")="R13w" : Reg16("R14")="R14w" : Reg16("R15")="R15w"

NewMap Reg8.s()
Reg8("Rax")="al" : Reg8("Rbx")="bl" : Reg8("Rcx")="cl" : Reg8("Rdx")="dl"
Reg8("Rsp")="spl" : Reg8("Rsi")="sil" : Reg8("Rbp")="bpl" : Reg8("Rdi")="dil"
Reg8("R8")="R8b" : Reg8("R9")="R9b" : Reg8("R10")="R10b" : Reg8("R11")="R11b"
Reg8("R12")="R12b" : Reg8("R13")="R13b" : Reg8("R14")="R14b" : Reg8("R15")="R15b"

ForEach Reg64()
  Debug "Macro BLSR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !BLSR "+Reg64()+", "+Reg64()
  Next
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro SHR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !SHR "+Reg64()+", 1"
  Next
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro MOV_"+Reg64()+"_Up_Down"
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  Debug "  !MOV "+Reg64()+", "+Reg64()
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  Debug "EndMacro"
  Debug ""
Next

Debug "Macro Set_CL1"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  ; cx = 1"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL8"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 8"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL64"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 64"
Debug "EndMacro"
Debug ""
Debug "Macro ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL1"
Debug "  MOVZX_Rcx"
Debug "  !MOVQ mm1, Rcx"
For Loop=1 To 16
  Debug "  !PSLLW mm0, mm1 ;"+Str(Loop)+" Left 1bit shift"
Next
Debug "  !MOVQ mm0, mm1"
For Roop=1 To 7
  For Loop=1 To 16
    Debug "  !PSLLW mm"+Str(Roop)+", mm0 ;"+Str(Loop)+" Left 1bit shift"
  Next
Next
Debug "EndMacro"
Debug ""

Macro SIMPLE_MOVE_REGISTERS_Up_and_Down
ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
EndMacro

Debug "Macro MOVZX_Rcx"
Debug "  !MOVZX cx, cl"
Debug "  !MOVZX Rcx, cl"
Debug "  !MOVZX cx, cl"
Debug "EndMacro"
Debug ""

Macro BeforeProcedureRegisters_1st
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64A() : Loop + 1 : Next
 EndMacro
 
Macro BeforeProcedureRegisters_2nd
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ "+Reg64A()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Debug "  ;"
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64B() : Loop + 1 : Next
EndMacro

Macro BeforeProcedureRegisters_3rd
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ "+Reg64B()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Debug "  !EMMS"
EndMacro
  
Macro BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_RDSEED_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
Macro BeforeProcedureRegisters_RDSEED_SHR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
;- Start
Debug ";- PureBasicStart"
BeforeProcedureRegisters_RDSEED_SHR
Debug "If OpenConsole("+Chr(34)+"MajiorityCamisole ES112 setup To General-purpose 64-bit registers."+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"-"+Chr(34)+")"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !StartStabilizer:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  PrintN("+Chr(34)+"Setup 1... SMSW BLSRx64 CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 2... RDSEED BLSRx64 CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 3... Logical to Physical CPU reg. Balancer"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
For Roop=1 To 64
  Debug "  ; "+Str(Roop)+" Setup"
  BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_RDSEED_BLSR
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  Debug "  BLSR_Rcx_x64"
  Debug "  Set_CL64"
  Debug "  MOVZX_Rcx"
  Debug "  !NOP QWORD [Rip+16]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !CALL QWORD Sleep"
  Debug "  !NOP QWORD [Rip-32]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  !RDRAND Rcx
  !CALL QWORD PB_RandomSeed
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
Next
SortList(Reg64(), #PB_Sort_Ascending)
SortList(Reg64A(), #PB_Sort_Ascending)
SortList(Reg64B(), #PB_Sort_Ascending)
BeforeProcedureRegisters_SMSW_BLSR
BeforeProcedureRegisters_RDSEED_BLSR
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  PrintN("+Chr(34)+"Finished"+Chr(34)+")"
Debug "  BLSR_Rax_x64"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL64"
Debug "  MOVZX_Rcx"
Debug "  !MOV Rax, Rcx"
Debug "  Set_CL8"
Debug "  !SHL Rax, cl"
Debug "  !MOV Rcx, Rax"
Debug "  !NOP QWORD [Rip+16]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !CALL QWORD Sleep"
Debug "  !NOP QWORD [Rip-32]"
BeforeProcedureRegisters_RDSEED_SHR
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JMP QWORD StartStabilizer"
Debug "  CloseConsole()"
Debug "EndIf"
Debug "Sleep_(0)"
Debug "End"
CallDebugger
End
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Caronte3D
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Re: Japanese ANIME quality up on streming

Post by Caronte3D »

I understand nothing :P :lol:
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Fred
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Re: Japanese ANIME quality up on streming

Post by Fred »

It's oryaaaaa magic, since 2004 :D
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Re: Japanese ANIME quality up on streming

Post by dige »

I'm impressed by oryaaaaa's ideas - but I don't understand what the code does. . :? :D
"Daddy, I'll run faster, then it is not so far..."
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Kiffi
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Re: Japanese ANIME quality up on streming

Post by Kiffi »

The code only works if you compile it under a full moon.
Hygge
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Mindphazer
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Re: Japanese ANIME quality up on streming

Post by Mindphazer »

Kiffi wrote: Mon Jan 29, 2024 11:14 am The code only works if you compile it under a full moon.
But be careful, there's a good chance you'll turn into a werewolf. :mrgreen:
MacBook Pro 16" M4 Pro - 24 Gb - MacOS 15.4.1 - Iphone 15 Pro Max - iPad at home
...and unfortunately... Windows at work...
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Re: Japanese ANIME quality up on streming

Post by threedslider »

It is a bit esoteric but yeah great work ! :mrgreen:
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oryaaaaa
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MajiorityCamisole 152 release

Post by oryaaaaa »

base code is 117. add BZHI initialize.
this effects depend sine waved delays for audio solutions.

This code depend BMI-2 instructions.
MOV r8, -1 : MOV r9, 0 : MOV rax, -1 : BZHI rax, r8, r9
result rax is null

Code: Select all

Debug "; MajiorityCamisole 152 (2023 03 17)"
Debug "; RDSEED LZCNT BLSRx64 BZHI CPU reg. Stabilizer for any voltage problems"
Debug "; Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"
Debug "; Design based by Military LAB-AI designed (Customized  Hiroyuki Yokota)"
Debug ""
Debug "MessageRequester("+Chr(34)+"END"+Chr(34)+","+Chr(34)+"Compiler options Executable Format Console And CPU With MMX"+Chr(34)+") : End"
Debug ""
!extrn PB_RandomSeed

Global NewList Reg64.s()
AddElement(Reg64()) : Reg64() ="Rax" : AddElement(Reg64()) : Reg64() ="Rbx"
AddElement(Reg64()) : Reg64() ="Rcx" : AddElement(Reg64()) : Reg64() ="Rdx"
AddElement(Reg64()) : Reg64() ="Rsp" : AddElement(Reg64()) : Reg64() ="Rsi"
AddElement(Reg64()) : Reg64() ="Rbp" : AddElement(Reg64()) : Reg64() ="Rdi"
AddElement(Reg64()) : Reg64() ="R8" : AddElement(Reg64()) : Reg64() ="R9"
AddElement(Reg64()) : Reg64() ="R10" : AddElement(Reg64()) : Reg64() ="R11"
AddElement(Reg64()) : Reg64() ="R12" : AddElement(Reg64()) : Reg64() ="R13"
AddElement(Reg64()) : Reg64() ="R14" : AddElement(Reg64()) : Reg64() ="R15"

Global NewList Reg64A.s()
AddElement(Reg64A()) : Reg64A() ="Rax" : AddElement(Reg64A()) : Reg64A() ="Rdx"
AddElement(Reg64A()) : Reg64A() ="Rsp" : AddElement(Reg64A()) : Reg64A() ="Rsi"
AddElement(Reg64A()) : Reg64A() ="R9" : AddElement(Reg64A()) : Reg64A() ="R11"
AddElement(Reg64A()) : Reg64A() ="R13" : AddElement(Reg64A()) : Reg64A() ="R15"

Global NewList Reg64B.s()
AddElement(Reg64B()) : Reg64B() ="Rbx" : AddElement(Reg64B()) : Reg64B() ="Rcx"
AddElement(Reg64B()) : Reg64B() ="Rbp" : AddElement(Reg64B()) : Reg64B() ="Rdi"
AddElement(Reg64B()) : Reg64B() ="R8" : AddElement(Reg64B()) : Reg64B() ="R10"
AddElement(Reg64B()) : Reg64B() ="R12" : AddElement(Reg64B()) : Reg64B() ="R14"

!RDRAND Rcx
!CALL QWORD PB_RandomSeed
RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())

NewMap Reg16.s()
Reg16("Rax")="ax" : Reg16("Rbx")="bx" : Reg16("Rcx")="cx" : Reg16("Rdx")="dx"
Reg16("Rsp")="sp" : Reg16("Rsi")="si" : Reg16("Rbp")="bp" : Reg16("Rdi")="di"
Reg16("R8")="R8w" : Reg16("R9")="R9w" : Reg16("R10")="R10w" : Reg16("R11")="R11w"
Reg16("R12")="R12w" : Reg16("R13")="R13w" : Reg16("R14")="R14w" : Reg16("R15")="R15w"

NewMap Reg8.s()
Reg8("Rax")="al" : Reg8("Rbx")="bl" : Reg8("Rcx")="cl" : Reg8("Rdx")="dl"
Reg8("Rsp")="spl" : Reg8("Rsi")="sil" : Reg8("Rbp")="bpl" : Reg8("Rdi")="dil"
Reg8("R8")="R8b" : Reg8("R9")="R9b" : Reg8("R10")="R10b" : Reg8("R11")="R11b"
Reg8("R12")="R12b" : Reg8("R13")="R13b" : Reg8("R14")="R14b" : Reg8("R15")="R15b"

ForEach Reg64()
  Debug "Macro BLSR_"+Reg64()+"_x64"
  Debug "  !LZCNT "+Reg64()+", "+Reg64()
  For Loop=1 To 64
    Debug "  !BLSR "+Reg64()+", "+Reg64()
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro SHR_"+Reg64()+"_x64"
  Debug "  !LZCNT "+Reg64()+", "+Reg64()
  For Loop=1 To 64
    Debug "  !SHR "+Reg64()+", 1"
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro MOV_"+Reg64()+"_Up_Down"
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  Debug "  !MOV "+Reg64()+", "+Reg64()
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  Debug "EndMacro"
  Debug ""
Next

Debug "Macro Set_CL1"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  ; cx = 1"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL8"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 8"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL64"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 64"
Debug "EndMacro"
Debug ""
Debug "Macro ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL1"
Debug "  MOVZX_Rcx"
Debug "  !MOVQ mm1, Rcx"
For Loop=1 To 16
  Debug "  !PSLLW mm0, mm1 ;"+Str(Loop)+" Left 1bit shift"
Next
Debug "  !MOVQ mm0, mm1"
For Roop=1 To 7
  For Loop=1 To 16
    Debug "  !PSLLW mm"+Str(Roop)+", mm0 ;"+Str(Loop)+" Left 1bit shift"
  Next
Next
Debug "EndMacro"
Debug ""

Macro SIMPLE_MOVE_REGISTERS_Up_and_Down
ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
EndMacro

Debug "Macro MOVZX_Rcx"
Debug "  !MOVZX cx, cl"
Debug "  !MOVZX Rcx, cl"
Debug "  !MOVZX cx, cl"
Debug "EndMacro"
Debug ""

Macro BeforeProcedureRegisters_1st
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64A() : Loop + 1 : Next
 EndMacro
 
Macro BeforeProcedureRegisters_2nd
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ "+Reg64A()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Debug "  ;"
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64B() : Loop + 1 : Next
EndMacro

Macro BeforeProcedureRegisters_3rd
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ "+Reg64B()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Debug "  !EMMS"
EndMacro
  
Macro BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_RDSEED_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
Macro BeforeProcedureRegisters_RDSEED_SHR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
;- Start
Debug ";- PureBasicStart"
BeforeProcedureRegisters_RDSEED_SHR
Debug "If OpenConsole("+Chr(34)+"MajiorityCamisole 152 setup To General-purpose 64-bit registers."+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"-"+Chr(34)+")"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !StartStabilizer:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !RDRAND R8"
Debug "  !LZCNT R8, R8"
Debug "  !RDRAND R9"
Debug "  !LZCNT R9, R9"
Debug "  !MOV R8, R8"
Debug "  !MOV R8w, R8w"
Debug "  !MOV R8b, R8b"
Debug "  !MOV R9, R9"
Debug "  !MOV R9w, R9w"
Debug "  !MOV R9b, R9b"
Debug "  !CMP R8b, R9b"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JZ QWORD StartStabilizer_in"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
;
Debug "  PrintN("+Chr(34)+"Delay process 16384 ms"+Chr(34)+")"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !MOV cl, 0"
Debug "  !MOV ch, 64"
Debug "  !MOV cl, cl"
Debug "  !MOV ch, ch"
Debug "  !MOV cx, cx"
Debug "  !MOVZX Rcx, cx"
Debug "  !NOP QWORD [Rip+16]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !CALL QWORD Sleep"
Debug "  !NOP QWORD [Rip-32]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JMP QWORD StartStabilizer"
;
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !StartStabilizer_in:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  PrintN("+Chr(34)+"Setup 1... SMSW LZCNT BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 2... RDSEED LZCNT BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 3... Logical to Physical CPU reg. Balancer"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Global SineWave.i, SineBits.i, SineAngels.i, CountBits.i, CountChk.i
; totalWave = 19,356 ms
For SineAngels=1 To 178 Step 6
  CountChk = 0
  Debug "  ; "+Str(SineAngels)+" Setup"
  BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_RDSEED_BLSR
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  Debug "  BLSR_Rcx_x64"
  Debug "  BLSR_R8_x64"
  SineWave = Abs(Round(Sin(Radian(SineAngels))*1000, #PB_Round_Nearest))
  !MOV Rax, [v_SineWave]
  !MOV R8, Rax
  !MOV [v_SineBits], R8
  Debug "; "+Str(SineWave)
  totalWave.i + SineWave
  Debug  "  !INC cl"
  For CountBits=63 To 1 Step -1
    If SineBits&(2<<CountBits)
      CountChk+1
      Debug  "  !INC R8b"
      Debug  "  !SHL R8, cl"
    ElseIf CountChk
      Debug  "  !SHL R8, cl"
    EndIf  
  Next
  If SineBits&2
    Debug  "  !INC R8b"
    Debug  "  !SHL R8, cl"
  Else
    Debug  "  !SHL R8, cl"
  EndIf  
  If SineBits&1
    Debug  "  !INC R8b"
  EndIf
  Debug "  !XCHG Rcx, R8"
  Debug "  !NOP QWORD [Rip+16]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !CALL QWORD Sleep"
  Debug "  !NOP QWORD [Rip-32]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  !RDRAND Rcx
  !CALL QWORD PB_RandomSeed
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
Next
SortList(Reg64(), #PB_Sort_Ascending)
SortList(Reg64A(), #PB_Sort_Ascending)
SortList(Reg64B(), #PB_Sort_Ascending)
BeforeProcedureRegisters_SMSW_BLSR
BeforeProcedureRegisters_RDSEED_BLSR
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  PrintN("+Chr(34)+"Finished"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JMP QWORD StartStabilizer"
Debug "  CloseConsole()"
Debug "EndIf"
Debug "Sleep_(0)"
Debug "End"
CallDebugger
End
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oryaaaaa
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MajiorityCamisole 153 release

Post by oryaaaaa »

Thank you your comments.

base code is 114. this code depend BMI-2 instructions.
for Streaming Videos or Gaming servers or Satelite broadcast servers
Thank you Intel secret services!
BZHI same registers only, you can write codes.

Code: Select all

Debug "; MajiorityCamisole 153 (2023 03 17)"
Debug "; RDSEED BLSRx64 BZHI CPU reg. Stabilizer for any voltage problems"
Debug "; Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"
Debug "; Design based by Military LAB-AI designed (Customized  Hiroyuki Yokota)"
Debug ""
Debug "MessageRequester("+Chr(34)+"END"+Chr(34)+","+Chr(34)+"Compiler options Executable Format Console And CPU With MMX"+Chr(34)+") : End"
Debug ""
!extrn PB_RandomSeed

Global NewList Reg64.s()
AddElement(Reg64()) : Reg64() ="Rax" : AddElement(Reg64()) : Reg64() ="Rbx"
AddElement(Reg64()) : Reg64() ="Rcx" : AddElement(Reg64()) : Reg64() ="Rdx"
AddElement(Reg64()) : Reg64() ="Rsp" : AddElement(Reg64()) : Reg64() ="Rsi"
AddElement(Reg64()) : Reg64() ="Rbp" : AddElement(Reg64()) : Reg64() ="Rdi"
AddElement(Reg64()) : Reg64() ="R8" : AddElement(Reg64()) : Reg64() ="R9"
AddElement(Reg64()) : Reg64() ="R10" : AddElement(Reg64()) : Reg64() ="R11"
AddElement(Reg64()) : Reg64() ="R12" : AddElement(Reg64()) : Reg64() ="R13"
AddElement(Reg64()) : Reg64() ="R14" : AddElement(Reg64()) : Reg64() ="R15"

Global NewList Reg64A.s()
AddElement(Reg64A()) : Reg64A() ="Rax" : AddElement(Reg64A()) : Reg64A() ="Rdx"
AddElement(Reg64A()) : Reg64A() ="Rsp" : AddElement(Reg64A()) : Reg64A() ="Rsi"
AddElement(Reg64A()) : Reg64A() ="R9" : AddElement(Reg64A()) : Reg64A() ="R11"
AddElement(Reg64A()) : Reg64A() ="R13" : AddElement(Reg64A()) : Reg64A() ="R15"

Global NewList Reg64B.s()
AddElement(Reg64B()) : Reg64B() ="Rbx" : AddElement(Reg64B()) : Reg64B() ="Rcx"
AddElement(Reg64B()) : Reg64B() ="Rbp" : AddElement(Reg64B()) : Reg64B() ="Rdi"
AddElement(Reg64B()) : Reg64B() ="R8" : AddElement(Reg64B()) : Reg64B() ="R10"
AddElement(Reg64B()) : Reg64B() ="R12" : AddElement(Reg64B()) : Reg64B() ="R14"

!RDRAND Rcx
!CALL QWORD PB_RandomSeed
RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())

NewMap Reg16.s()
Reg16("Rax")="ax" : Reg16("Rbx")="bx" : Reg16("Rcx")="cx" : Reg16("Rdx")="dx"
Reg16("Rsp")="sp" : Reg16("Rsi")="si" : Reg16("Rbp")="bp" : Reg16("Rdi")="di"
Reg16("R8")="R8w" : Reg16("R9")="R9w" : Reg16("R10")="R10w" : Reg16("R11")="R11w"
Reg16("R12")="R12w" : Reg16("R13")="R13w" : Reg16("R14")="R14w" : Reg16("R15")="R15w"

NewMap Reg8.s()
Reg8("Rax")="al" : Reg8("Rbx")="bl" : Reg8("Rcx")="cl" : Reg8("Rdx")="dl"
Reg8("Rsp")="spl" : Reg8("Rsi")="sil" : Reg8("Rbp")="bpl" : Reg8("Rdi")="dil"
Reg8("R8")="R8b" : Reg8("R9")="R9b" : Reg8("R10")="R10b" : Reg8("R11")="R11b"
Reg8("R12")="R12b" : Reg8("R13")="R13b" : Reg8("R14")="R14b" : Reg8("R15")="R15b"

ForEach Reg64()
  Debug "Macro BLSR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !BLSR "+Reg64()+", "+Reg64()
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro SHR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !SHR "+Reg64()+", 1"
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro MOV_"+Reg64()+"_Up_Down"
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  Debug "  !MOV "+Reg64()+", "+Reg64()
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  Debug "EndMacro"
  Debug ""
Next

Debug "Macro Set_CL1"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  ; cx = 1"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL8"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 8"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL64"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 64"
Debug "EndMacro"
Debug ""
Debug "Macro ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL1"
Debug "  MOVZX_Rcx"
Debug "  !MOVQ mm1, Rcx"
For Loop=1 To 16
  Debug "  !PSLLW mm0, mm1 ;"+Str(Loop)+" Left 1bit shift"
Next
Debug "  !MOVQ mm0, mm1"
For Roop=1 To 7
  For Loop=1 To 16
    Debug "  !PSLLW mm"+Str(Roop)+", mm0 ;"+Str(Loop)+" Left 1bit shift"
  Next
Next
Debug "EndMacro"
Debug ""

Macro SIMPLE_MOVE_REGISTERS_Up_and_Down
ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
EndMacro

Debug "Macro MOVZX_Rcx"
Debug "  !MOVZX cx, cl"
Debug "  !MOVZX Rcx, cl"
Debug "  !MOVZX cx, cl"
Debug "EndMacro"
Debug ""

Macro BeforeProcedureRegisters_1st
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64A() : Loop + 1 : Next
 EndMacro
 
Macro BeforeProcedureRegisters_2nd
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ "+Reg64A()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Debug "  ;"
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64B() : Loop + 1 : Next
EndMacro

Macro BeforeProcedureRegisters_3rd
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ "+Reg64B()+", mm"+Str(Loop) : Loop + 1 : Next
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Debug "  !EMMS"
EndMacro
  
Macro BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !SMSW "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_RDSEED_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
Macro BeforeProcedureRegisters_RDSEED_SHR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro
  
;- Start
Debug ";- PureBasicStart"
BeforeProcedureRegisters_RDSEED_SHR
Debug "If OpenConsole("+Chr(34)+"MajiorityCamisole 153 setup To General-purpose 64-bit registers."+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa)"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"-"+Chr(34)+")"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !StartStabilizer:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  PrintN("+Chr(34)+"Setup 1... SMSW BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 2... RDSEED BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 3... Logical to Physical CPU reg. Balancer"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Global SineWave.i, SineBits.i, SineAngels.i, CountBits.i, CountChk.i
; totalWave = 114581
For SineAngels=1 To 178
  CountChk = 0
  Debug "  ; "+Str(SineAngels)+" Setup"
  BeforeProcedureRegisters_SMSW_BLSR
  BeforeProcedureRegisters_RDSEED_BLSR
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  Debug "  BLSR_Rcx_x64"
  Debug "  BLSR_R8_x64"
  SineWave = Abs(Round(Sin(Radian(SineAngels))*1000, #PB_Round_Nearest))
  !MOV Rax, [v_SineWave]
  !MOV R8, Rax
  !MOV [v_SineBits], R8
  Debug "; "+Str(SineWave)
  totalWave.i + SineWave
  Debug  "  !INC cl"
  For CountBits=63 To 1 Step -1
    If SineBits&(2<<CountBits)
      CountChk+1
      Debug  "  !INC R8b"
      Debug  "  !SHL R8, cl"
    ElseIf CountChk
      Debug  "  !SHL R8, cl"
    EndIf  
  Next
  If SineBits&2
    Debug  "  !INC R8b"
    Debug  "  !SHL R8, cl"
  Else
    Debug  "  !SHL R8, cl"
  EndIf  
  If SineBits&1
    Debug  "  !INC R8b"
  EndIf
  Debug "  !XCHG Rcx, R8"
  Debug "  !NOP QWORD [Rip+16]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !CALL QWORD Sleep"
  Debug "  !NOP QWORD [Rip-32]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  !RDRAND Rcx
  !CALL QWORD PB_RandomSeed
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
Next
SortList(Reg64(), #PB_Sort_Ascending)
SortList(Reg64A(), #PB_Sort_Ascending)
SortList(Reg64B(), #PB_Sort_Ascending)
BeforeProcedureRegisters_SMSW_BLSR
BeforeProcedureRegisters_RDSEED_BLSR
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  PrintN("+Chr(34)+"Finished"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JMP QWORD StartStabilizer"
Debug "  CloseConsole()"
Debug "EndIf"
Debug "Sleep_(0)"
Debug "End"
CallDebugger
End
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NicTheQuick
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Re: Japanese ANIME quality up on streming

Post by NicTheQuick »

Dafuq is this?
The english grammar is freeware, you can use it freely - But it's not Open Source, i.e. you can not change it or publish it in altered way.
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Caronte3D
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Joined: Fri Jan 22, 2016 5:33 pm
Location: Some Universe

Re: Japanese ANIME quality up on streming

Post by Caronte3D »

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oryaaaaa
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Posts: 825
Joined: Mon Jan 12, 2004 11:40 pm
Location: Okazaki, JAPAN

Re: Japanese ANIME quality up on streming

Post by oryaaaaa »

VOICE "PLEASE UPLOAD NEW ML2 source code"


My new homepage here
https://www.mics.ne.jp/~ai_closed_mynet/
Download Executables, but ... very dangerus power kick from SYSTEM for military.
You should use for AUDIO VIDEO PRINT PHOTO WEBhost only, don't use any in LABs.

This "MajiorityLabyrinth 2" is super low-digital-noise process for intel CPU 13th 14th

CPU 13th 14th keep codes some rules.
1. Don't remove "NOP QWORD [Rip] x2 lines" CPU power management brake down
2. Don't remove "XCHG al, ah ... dh, dl , XCHG spl, spl after NOP" same reason
If you can try crush CPU, You should hear CPU fan motor noise. boom ? RESET!
This troubles is not depend 13th 14th only, others Skylake CometLake any crushed

but more quality for Anime Video Streaming is BEST solution.
I test Core i7-13700 (13th Rapter) and Core i5-6200U (Skylake)
ThinkPad Yoga 260 sound use conexant digital amplifier chips, very exciting sound.

Code: Select all

Debug "; MajiorityLabyrinth 2 (2024 08 14)"
Debug "; RDSEED CRC32 BLSRx64 BZHI CPU reg. Stabilizer from JAPAN"
Debug "; Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa) 444-3174"
Debug "; Design based by Military LAB-AI designed (Customized  Hiroyuki Yokota)"
Debug ""
Debug "MessageRequester("+Chr(34)+"END"+Chr(34)+","+Chr(34)+"Compiler options Executable Format Console And CPU With MMX"+Chr(34)+") : End"
Debug ""
!extrn PB_RandomSeed

; ; ; ; ; ; ; ; Intel® 64 And IA-32 ArchitecturesSoftware Developer’s Manual
; ; ; ; ; ; ; ; Volume 2 (2A, 2B, 2C, & 2D):Instruction Set Reference, A-Z
; ; ; ; ; ; ; ; Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix)
; ; ; ; ; ; ; ; 
; ; ; ; ; ; ; ; ALNone0AXNone0EAXNone0RAXNone0
; ; ; ; ; ; ; ; DLNone2DXNone2EDXNone2RDXNone2
; ; ; ; ; ; ; ; SPLYes 4SPNone4ESPNone4RSPNone4
; ; ; ; ; ; ; ; SILYes6SINone6ESINone6RSINone6
; ; ; ; ; ; ; ; R8BYes0R8WYes0R8DYes0R8Yes0
; ; ; ; ; ; ; ; R10BYes2R10WYes2R10DYes2R10Yes2
; ; ; ; ; ; ; ; R12BYes4R12WYes4R12DYes4R12Yes4
; ; ; ; ; ; ; ; R14BYes6R14WYes6R14DYes6R14Yes6
; ; ; ; ; ; ; ; 
; ; ; ; ; ; ; ; CLNone1CXNone1ECXNone1RCXNone1
; ; ; ; ; ; ; ; BLNone3BXNone3EBXNone3RBXNone3
; ; ; ; ; ; ; ; BPLYes5BPNone5EBPNone5RBPNone5
; ; ; ; ; ; ; ; DILYes7DINone7EDINone7RDINone7
; ; ; ; ; ; ; ; R9BYes1R9WYes1R9DYes1R9Yes1
; ; ; ; ; ; ; ; R11BYes3R11WYes3R11DYes3R11Yes3
; ; ; ; ; ; ; ; R13BYes5R13WYes5R13DYes5R13Yes5
; ; ; ; ; ; ; ; R15BYes7R15WYes7R15DYes7R15Yes7

Global NewList Reg64.s()
AddElement(Reg64()) : Reg64() ="Rax" : AddElement(Reg64()) : Reg64() ="Rbx"
AddElement(Reg64()) : Reg64() ="Rcx" : AddElement(Reg64()) : Reg64() ="Rdx"
AddElement(Reg64()) : Reg64() ="Rsp" : AddElement(Reg64()) : Reg64() ="Rsi"
AddElement(Reg64()) : Reg64() ="Rbp" : AddElement(Reg64()) : Reg64() ="Rdi"
AddElement(Reg64()) : Reg64() ="R8" : AddElement(Reg64()) : Reg64() ="R9"
AddElement(Reg64()) : Reg64() ="R10" : AddElement(Reg64()) : Reg64() ="R11"
AddElement(Reg64()) : Reg64() ="R12" : AddElement(Reg64()) : Reg64() ="R13"
AddElement(Reg64()) : Reg64() ="R14" : AddElement(Reg64()) : Reg64() ="R15"

Global NewList Reg64A.s()
AddElement(Reg64A()) : Reg64A() ="Rax" : AddElement(Reg64A()) : Reg64A() ="Rdx"
AddElement(Reg64A()) : Reg64A() ="Rsp" : AddElement(Reg64A()) : Reg64A() ="Rsi"
AddElement(Reg64A()) : Reg64A() ="R8" : AddElement(Reg64A()) : Reg64A() ="R10"
AddElement(Reg64A()) : Reg64A() ="R12" : AddElement(Reg64A()) : Reg64A() ="R14"

Global NewList Reg64B.s()
AddElement(Reg64B()) : Reg64B() ="Rbx" : AddElement(Reg64B()) : Reg64B() ="Rcx"
AddElement(Reg64B()) : Reg64B() ="Rbp" : AddElement(Reg64B()) : Reg64B() ="Rdi"
AddElement(Reg64B()) : Reg64B() ="R9" : AddElement(Reg64B()) : Reg64B() ="R11"
AddElement(Reg64B()) : Reg64B() ="R13" : AddElement(Reg64B()) : Reg64B() ="R15"

!RDRAND Rcx
!ROR Rcx, 1
!ROR Rcx, 1
!CALL QWORD PB_RandomSeed
RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())

NewMap Reg16.s()
Reg16("Rax")="ax" : Reg16("Rbx")="bx" : Reg16("Rcx")="cx" : Reg16("Rdx")="dx"
Reg16("Rsp")="sp" : Reg16("Rsi")="si" : Reg16("Rbp")="bp" : Reg16("Rdi")="di"
Reg16("R8")="R8w" : Reg16("R9")="R9w" : Reg16("R10")="R10w" : Reg16("R11")="R11w"
Reg16("R12")="R12w" : Reg16("R13")="R13w" : Reg16("R14")="R14w" : Reg16("R15")="R15w"

NewMap Reg8.s()
Reg8("Rax")="al" : Reg8("Rbx")="bl" : Reg8("Rcx")="cl" : Reg8("Rdx")="dl"
Reg8("Rsp")="spl" : Reg8("Rsi")="sil" : Reg8("Rbp")="bpl" : Reg8("Rdi")="dil"
Reg8("R8")="R8b" : Reg8("R9")="R9b" : Reg8("R10")="R10b" : Reg8("R11")="R11b"
Reg8("R12")="R12b" : Reg8("R13")="R13b" : Reg8("R14")="R14b" : Reg8("R15")="R15b"

ForEach Reg64()
  Debug "Macro BLSR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !BLSR "+Reg64()+", "+Reg64()
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro SHR_"+Reg64()+"_x64"
  For Loop=1 To 64
    Debug "  !SHR "+Reg64()+", 1"
  Next
  Debug "  !BZHI "+Reg64()+", "+Reg64()+", "+Reg64()
  Debug "EndMacro"
  Debug ""
Next

ForEach Reg64()
  Debug "Macro MOV_"+Reg64()+"_Up_Down"
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  Debug "  !MOV "+Reg64()+", "+Reg64()
  Debug "  !MOV "+Reg16(Reg64())+", "+Reg16(Reg64())
  If Len(Reg8(Reg64()))=2
    Debug "  !MOV "+ReplaceString(Reg8(Reg64()), "l", "h")+", "+ReplaceString(Reg8(Reg64()), "l", "h")
  EndIf
  Debug "  !MOV "+Reg8(Reg64())+", "+Reg8(Reg64())
  Debug "EndMacro"
  Debug ""
Next

Debug "Macro Set_CL1"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  ; cx = 1"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL8"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 8"
Debug "EndMacro"
Debug ""
Debug "Macro Set_CL64"
Debug "  BLSR_Rcx_x64"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL cl, cl"
Debug "  ; cx = 64"
Debug "EndMacro"
Debug ""
Debug "Macro ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  BLSR_Rcx_x64"
Debug "  Set_CL1"
Debug "  MOVZX_Rcx"
Debug "  !MOVQ mm1, Rcx"
For Loop=1 To 16
  Debug "  !PSLLW mm0, mm1 ;"+Str(Loop)+" Left 1bit shift"
Next
Debug "  !MOVQ mm0, mm1"
For Roop=1 To 7
  For Loop=1 To 16
    Debug "  !PSLLW mm"+Str(Roop)+", mm0 ;"+Str(Loop)+" Left 1bit shift"
  Next
Next
Debug "EndMacro"
Debug ""

Macro SIMPLE_MOVE_REGISTERS_Up_and_Down
    RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
    ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
    ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
EndMacro

Debug "Macro MOVZX_Rcx"
Debug "  !MOVZX cx, cl"
Debug "  !MOVZX Rcx, cl"
Debug "  !MOVZX cx, cl"
Debug "EndMacro"
Debug ""

Macro BeforeProcedureRegisters_1st
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64A() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64A() : Loop + 1 : Next
  Debug "!MOVQ mm0, mm0"
  Debug "!MOVQ mm1, mm1"
  Debug "!MOVQ mm2, mm2"
  Debug "!MOVQ mm3, mm3"
  Debug "!MOVQ mm4, mm4"
  Debug "!MOVQ mm5, mm5"
  Debug "!MOVQ mm6, mm6"
  Debug "!MOVQ mm7, mm7"
 EndMacro
 
Macro BeforeProcedureRegisters_2nd
  Loop=0
  Debug "!MOVQ mm0, mm0"
  Debug "!MOVQ mm1, mm1"
  Debug "!MOVQ mm2, mm2"
  Debug "!MOVQ mm3, mm3"
  Debug "!MOVQ mm4, mm4"
  Debug "!MOVQ mm5, mm5"
  Debug "!MOVQ mm6, mm6"
  Debug "!MOVQ mm7, mm7"
  ForEach Reg64A() : Debug "  !MOVQ "+Reg64A()+", mm"+Str(Loop) : Loop + 1 : Next
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
  ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Debug "  ;"
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Loop=0
  ForEach Reg64B() : Debug "  !MOVQ mm"+Str(Loop)+", "+Reg64B() : Loop + 1 : Next
  Debug "!MOVQ mm0, mm0"
  Debug "!MOVQ mm1, mm1"
  Debug "!MOVQ mm2, mm2"
  Debug "!MOVQ mm3, mm3"
  Debug "!MOVQ mm4, mm4"
  Debug "!MOVQ mm5, mm5"
  Debug "!MOVQ mm6, mm6"
  Debug "!MOVQ mm7, mm7"
EndMacro

Macro BeforeProcedureRegisters_3rd
  Loop=0
  Debug "!MOVQ mm0, mm0"
  Debug "!MOVQ mm1, mm1"
  Debug "!MOVQ mm2, mm2"
  Debug "!MOVQ mm3, mm3"
  Debug "!MOVQ mm4, mm4"
  Debug "!MOVQ mm5, mm5"
  Debug "!MOVQ mm6, mm6"
  Debug "!MOVQ mm7, mm7"
  ForEach Reg64B() : Debug "  !MOVQ "+Reg64B()+", mm"+Str(Loop) : Loop + 1 : Next
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
  ForEach Reg64B() : Debug "  MOV_"+Reg64B()+"_Up_Down" : Next
  Debug "  !EMMS"
EndMacro

Macro BeforeProcedureRegisters_RDSEED_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_CRC32_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !CRC32 "+Reg64A()+", QWORD [Rip]"
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !CRC32 "+Reg64B()+", QWORD [Rip]"
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_MOVBE_BLSR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !MOVBE "+Reg64A()+", QWORD [Rip]"
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !MOVBE "+Reg64B()+", QWORD [Rip]"
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  BLSR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_RDSEED_SHR
  BeforeProcedureRegisters_1st
  ForEach Reg64A()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64A()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64A()+"_x64"
  Next
  BeforeProcedureRegisters_2nd
  ForEach Reg64B()
    Debug "  !NOP QWORD [Rip+16]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !RDSEED "+Reg64B()
    Debug "  !NOP QWORD [Rip-36]"
    Debug "  SHR_"+Reg64B()+"_x64"
  Next
  BeforeProcedureRegisters_3rd
EndMacro

Macro BeforeProcedureRegisters_NOP_EAX_BLSR
  For Loop=1 To 32
    Debug "  !BLSR Eax, Eax"
  Next
  Debug "  !BZHI Eax, Eax, Eax"
  For Loop=1 To 64
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP ax"
    Debug "  !NOP ax"
  Next
  For Loop=1 To 64
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP Eax"
    Debug "  !NOP Eax"
  Next
  For Loop=1 To 32
    Debug "  !BLSR Eax, Eax"
  Next
  Debug "  !BZHI Eax, Eax, Eax"
EndMacro

Macro BeforeProcedureRegisters_NOP_ESP_BLSR
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  ;   RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
  ;   ForEach Reg64A() : Debug "  MOV_"+Reg64A()+"_Up_Down" : Next
  Debug "!MOVQ mm5, Rsp"
  Debug "!MOVQ mm5, mm5"
  For Loop=1 To 32
    Debug "  !BLSR Esp, Esp"
  Next
  Debug "  !BZHI Esp, Esp, Esp"
  For Loop=1 To 64
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP sp"
    Debug "  !NOP sp"
  Next
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !XCHG bl, bh"
  Debug "  !XCHG bh, bl"
  Debug "  !XCHG cl, ch"
  Debug "  !XCHG ch, cl"
  Debug "  !XCHG al, ah"
  Debug "  !XCHG ah, al"
  Debug "  !XCHG dl, dh"
  Debug "  !XCHG dh, dl"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !XCHG spl, spl"
  Debug "  !MOVQ mm1, mm5"
  Debug "  !MOVQ mm2, mm1"
  Debug "  !MOVQ mm3, mm2"
  Debug "  !MOVQ mm4, mm3"
  Debug "  !MOVQ mm6, mm4"
  Debug "  !MOVQ mm7, mm6"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !XCHG al, ah"
  Debug "  !XCHG ah, al"
  Debug "  !XCHG dl, dh"
  Debug "  !XCHG dh, dl"
  Debug "  !XCHG bl, bh"
  Debug "  !XCHG bh, bl"
  Debug "  !XCHG cl, ch"
  Debug "  !XCHG ch, cl"
  For Loop=1 To 64
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP QWORD [Rip]"
    Debug "  !NOP Esp"
    Debug "  !NOP Esp"
  Next
  For Loop=1 To 32
    Debug "  !BLSR Esp, Esp"
  Next
  Debug "  !BZHI Esp, Esp, Esp"
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  Debug "  !MOVQ Rsp, mm7"
  Debug "  !EMMS"
EndMacro

Macro FXCACHE
  For Loop=0 To 504 Step 8
    Debug "  !NOP QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"]"
  Next
EndMacro
  
Macro FXSAVE
  ;   Debug "  !MOV R8, QWORD [p_FXSAVE]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !FXSAVE64 [R8]"
EndMacro

Macro FXRSTOR
  ; Debug "    !MOV R8, QWORD [p_FXSAVE] "
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !FXRSTOR64 [R8]"
EndMacro

Macro FXCLEAR_ALL
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ;   Debug "  !MOV R8, QWORD [p_FXSAVE2]"
  For Loop=-512 To -8 Step 8
    Debug "  !MOVNTQ QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"], mm5"
  Next
  For Loop=0 To 504 Step 8
    Debug "  !MOVNTQ QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"], mm5"
  Next
  For Loop=0 To 504 Step 8
    Debug "  !NOP QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"]"
  Next
  For Loop=512 To 1023 Step 8
    Debug "  !MOVNTQ QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"], mm5"
  Next
  Debug "  !EMMS"
EndMacro

Macro FXCLEAR_512
  Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
  ;   Debug "  !MOV R8, QWORD [p_FXSAVE2]"
  For Loop=0 To 504 Step 8
    Debug "  !MOVNTQ QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"], mm5"
  Next
  For Loop=0 To 504 Step 8
    Debug "  !NOP QWORD [R8"+ReplaceString("+"+Str(Loop), "+-", "-")+"]"
  Next
  Debug "  !EMMS"
EndMacro

Debug "  Set_CL64"
Debug "  !NOP QWORD [Rip+16]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !CALL QWORD Sleep"
Debug "  !NOP QWORD [Rip-32]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"

Debug "  Global *FXSAVE, *FXSAVE2"
Debug "  BLSR_Rcx_x64"
Debug "  BLSR_Rdx_x64"
Debug "  BLSR_R8_x64"
Debug "  !INC R8b"
Debug "  !INC R8b"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !MOV R8b, R8b"
Debug "  !MOV R8w, R8w"
Debug "  !MOV R8, R8"
Debug "  !SHL R8, cl" ; 16,384
Debug "  !XCHG Rcx, R8"
Debug "  !INC dl"
Debug "  !MOVZX Rdx, dl"
Debug "  !CALL PB_AllocateMemory2"
Debug "  BLSR_Rcx_x64"
Debug "  BLSR_R8_x64"
Debug "  !INC R8b"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL R8, cl" ; 8,192
Debug "  !MOV R8b, R8b"
Debug "  !MOV R8w, R8w"
Debug "  !MOV R8, R8"
Debug "  !MOV al, al"
Debug "  !MOV ah, ah"
Debug "  !MOV ax, ax"
Debug "  !MOV Rax, Rax"
Debug "  !ADD Rax, R8"
Debug "  !MOVNTI QWORD [p_FXSAVE], Rax"
Debug "  !NOP QWORD [p_FXSAVE]"
;  "*FXSAVE = AllocateMemory(16384,1) + 8192"
Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  !MOV R8, QWORD [p_FXSAVE]"
FXCLEAR_ALL
Debug "  BLSR_Rcx_x64"
Debug "  BLSR_Rdx_x64"
Debug "  BLSR_R8_x64"
Debug "  !INC R8b"
Debug "  !INC R8b"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !MOV R8b, R8b"
Debug "  !MOV R8w, R8w"
Debug "  !MOV R8, R8"
Debug "  !SHL R8, cl" ; 16,384
Debug "  !XCHG Rcx, R8"
Debug "  !INC dl"
Debug "  !MOVZX Rdx, dl"
Debug "  !CALL PB_AllocateMemory2"
Debug "  BLSR_Rcx_x64"
Debug "  BLSR_R8_x64"
Debug "  !INC R8b"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !INC cl"
Debug "  !SHL R8, cl" ; 8,192
Debug "  !MOV R8b, R8b"
Debug "  !MOV R8w, R8w"
Debug "  !MOV R8, R8"
Debug "  !MOV al, al"
Debug "  !MOV ah, ah"
Debug "  !MOV ax, ax"
Debug "  !MOV Rax, Rax"
Debug "  !ADD Rax, R8"
Debug "  !MOVNTI QWORD [p_FXSAVE2], Rax"
Debug "  !NOP QWORD [p_FXSAVE2]"
;  "*FXSAVE = AllocateMemory(16384,1) + 8192"
Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  !MOV R8, QWORD [p_FXSAVE2]"
FXCLEAR_ALL
  
;- Start
Debug ";- PureBasicStart"
BeforeProcedureRegisters_RDSEED_SHR
Debug "If OpenConsole("+Chr(34)+"MajiorityLabyrinth 2 setup To General-purpose 64-bit registers."+Chr(34)+")"
Debug "  Set_CL64"
Debug "  !NOP QWORD [Rip+16]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !CALL QWORD Sleep"
Debug "  !NOP QWORD [Rip-32]"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  PrintN("+Chr(34)+"Copyright (c) 2020-2024 Hiroyuki Yokota (oryaaaaa) 444-3174"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"-"+Chr(34)+")"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !StartStabilizer:"
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  PrintN("+Chr(34)+"Instruction CPU cache to TimeAPI ProfileAPI for multimedia timer."+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 1... NOP Reg32 BLSRx32 CPU reg. Expressions"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 2... MOVBE BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 3... CRC32 BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 4... RDSEED BLSRx64 BZHI CPU reg. Stabilizer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"Setup 5... Logical to Physical CPU reg. Balancer"+Chr(34)+")"
Debug "  PrintN("+Chr(34)+"[Loop 29 times] ... Setup + FXSAVE64 sleep_(sine wave) ...[End] FXRSTOR64"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Global SineWave.i, SineBits.i, SineAngels.i, CountBits.i, CountChk.i
; totalWave = 19,356 ms
For SineAngels=1 To 178 Step 6
  CountChk = 0
  Debug "  ; "+Str(SineAngels)+" Setup"
  BeforeProcedureRegisters_NOP_EAX_BLSR
  BeforeProcedureRegisters_NOP_ESP_BLSR
  BeforeProcedureRegisters_MOVBE_BLSR
  BeforeProcedureRegisters_CRC32_BLSR
  BeforeProcedureRegisters_RDSEED_BLSR
  SIMPLE_MOVE_REGISTERS_Up_and_Down
  Debug "    !MOV R8, QWORD [p_FXSAVE] "
  FXCACHE
  FXSAVE
  FXCACHE
  Debug "  BLSR_Rcx_x64"
  Debug "  BLSR_R8_x64"
  SineWave = Abs(Round(Sin(Radian(SineAngels))*1000, #PB_Round_Nearest))
  !MOV Rax, [v_SineWave]
  !MOV R8, Rax
  !MOV [v_SineBits], R8
  Debug "; "+Str(SineWave)
  totalWave.i + SineWave
  Debug  "  !INC cl"
  For CountBits=63 To 1 Step -1
    If SineBits&(2<<CountBits)
      CountChk+1
      Debug  "  !INC R8b"
      Debug  "  !SHL R8, cl"
    ElseIf CountChk
      Debug  "  !SHL R8, cl"
    EndIf  
  Next
  If SineBits&2
    Debug  "  !INC R8b"
    Debug  "  !SHL R8, cl"
  Else
    Debug  "  !SHL R8, cl"
  EndIf  
  If SineBits&1
    Debug  "  !INC R8b"
  EndIf
  Debug "  !MOV cl, R8b"
  Debug "  !MOV cx, R8w"
  Debug "  !MOV Rcx, R8"
  Debug "  !NOP QWORD [Rip+16]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !CALL QWORD Sleep"
  Debug "  !NOP QWORD [Rip-32]"
  Debug "  !NOP QWORD [Rip]"
  Debug "  !NOP QWORD [Rip]"
  !RDRAND Rcx
  !ROL Rcx, 1
  !ROL Rcx, 1
  !CALL QWORD PB_RandomSeed
  RandomizeList(Reg64()) : RandomizeList(Reg64A()) : RandomizeList(Reg64B())
Next
SortList(Reg64(), #PB_Sort_Ascending)
SortList(Reg64A(), #PB_Sort_Ascending)
SortList(Reg64B(), #PB_Sort_Ascending)
BeforeProcedureRegisters_NOP_EAX_BLSR
BeforeProcedureRegisters_NOP_ESP_BLSR
BeforeProcedureRegisters_MOVBE_BLSR
BeforeProcedureRegisters_CRC32_BLSR
BeforeProcedureRegisters_RDSEED_BLSR
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  !MOV R8, QWORD [p_FXSAVE]"
FXCACHE
FXRSTOR
Debug "  Swap *FXSAVE2, *FXSAVE"
Debug "  ALL_MMX_CLEAR_SHIFTWORD_INC_CL"
Debug "  !MOV R8, QWORD [p_FXSAVE]"
FXCLEAR_ALL
FXCACHE
Debug "  PrintN("+Chr(34)+"Finished"+Chr(34)+")"
SIMPLE_MOVE_REGISTERS_Up_and_Down
Debug "  !NOP QWORD [Rip]"
Debug "  !NOP QWORD [Rip]"
Debug "  !JMP QWORD StartStabilizer"
Debug "  CloseConsole()"
Debug "EndIf"
Debug "Sleep_(0)"
Debug "AllocateMemory(0,0)"
Debug "End"
CallDebugger
End
1. run
2. output "clipboard text"
3. paste New tab
4. cpu optimize MMX
5. remove message
6. run
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Kiffi
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Posts: 1484
Joined: Tue Mar 02, 2004 1:20 pm
Location: Amphibios 9

Re: Japanese ANIME quality up on streming

Post by Kiffi »

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Caronte3D
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Posts: 1355
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Re: Japanese ANIME quality up on streming

Post by Caronte3D »

:mrgreen: :mrgreen:
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